Please refer to FIGS. 1A and 1B that are schematic diagrams showing conventional personal computer structures. The core circuit of each of the computer structures comprises a microprocessor 10, a north bridge chip 11 and a south bridge chip 12. A system memory 13 communicates with the north bridge chip 11 via a memory bus. In FIG. 1A, a graphics chip separate from the north bridge chip is shown. The graphics chip is incorporated in a graphics card 14. The graphics card 14 is connected to the north bridge chip 11 via a PCI (Peripheral Component Interconnect) or AGP (Accelerated Graphics Port) bus, and comprises a graphics accelerator 141 and a local memory 142 specifically connected to and provided for the graphics accelerator 141. Alternatively, in the computer structure of FIG. 1B, the graphics accelerator 141 is integrated into the north bridge chip 11. Therefore, the local memory 142 is not present any longer, and in stead, a specified memory block 131 is defined in the system memory 13, which is referred to as an AGP memory, to perform the function of the local memory 142. The graphics accelerator 141 thus shares the memory bus between the north bridge chip 11 and the system memory 13 to communicate with the AGP memory 131.
The memory bus between the system memory 13 and the north bridge chip 11 is generally uni-channel structured, and has a data bandwidth of 64 bits. Such data transmission bandwidth, however, has been beyond practical requirement due to the significantly increasing data transmission quantity between the system memory 13 and the north bridge chip 11. The situation is even serious on the condition that the data transmission bandwidth of the memory bus has to be shared by the graphics accelerator 141 for accessing the AGP memory 131.